DLD 4-bit Adder Circuit Verilog Code | Modelsim

Block Diagram Verilog Code module FourBitAdder(c4,s3,s2,s1,s0,a3,b3,a2,b2,a1,b1,a0,b0,cin); input a3,b3,a2,b2,a1,b1,a0,b0,cin; output c4,s3,s2,s1,s0; wire c4,c3,c2,c1,s3,s2,s1,s0; FuAd FA1(c1,s0,a0,b0,cin); FuAd FA2(c2,s1,a1,b1,c1); FuAd FA3(c3,s2,a2,b2,c2); FuAd FA4(c4,s3,a3,b3,c3); endmodule module FuAd(cfa,sfa,a,b,cin); input a,b,cin; output cfa,sfa; wire ch1,sh1,ch2; HA h1(a,b, ch1,sh1); HA h2(sh1,cin, ch2,sfa); or o1(cfa,ch1,ch2); endmodule   module HA (A,B,C,S); input A,B; output C,S; xor a1(S,A,B); and a2(C,A,B); endmodule

module Stim_FourBitAdder; reg a3,b3,a2,b2,a1,b1,a0,b0,cin; wire c4,c3,c2,c1,s3,s2,s1,s0; FourBitAdder FBA(c4,s3,s2,s1,s0,a3,b3,a2,b2,a1,b1,a0,b0,cin);   initial begin     a3=1'b0; b3=1'b0; a2=1'b0; b2=1'b0; a1=1'b0; b1=1'b0; a0=1'b0; b0=1'b0; cin=1'b0; #50 a3=1'b0; b3=1'b0; a2=1'b0; b2=1'b0; a1=1'b1; b1=1'b1; a0=1'b1; b0=1'b1; #50 a3=1'b0; b3=1'b0; a2=1'b1; b2=1'b1; a1=1'b0; b1=1'b0; a0=1'b1; b0=1'b1; #50 a3=1'b0; b3=1'b0; a2=1'b1; b2=1'b1; a1=1'b1; b1=1'b1; a0=1'b0; b0=1'b0; #50 a3=1'b0; b3=1'b0; a2=1'b1; b2=1'b1; a1=1'b1; b1=1'b1; a0=1'b1; b0=1'b1; #50 a3=1'b1; b3=1'b1; a2=1'b0; b2=1'b0; a1=1'b0; b1=1'b0; a0=1'b0; b0=1'b0; #50 a3=1'b1; b3=1'b1; a2=1'b1; b2=1'b1; a1=1'b0; b1=1'b0; a0=1'b0; b0=1'b0; #50 a3=1'b1; b3=1'b1; a2=1'b1; b2=1'b1; a1=1'b1; b1=1'b1; a0=1'b1; b0=1'b1;  #50 a3=1'b1; b3=1'b1; a2=1'b1; b2=1'b1; a1=1'b1; b1=1'b1; a0=1'b1; b0=1'b1; end endmodule Timing Diagram of Above Code

 

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